Hardware Architectures for Lazy Functional Programming Revisited
Find out more about subscribing to add all events.
Hardware Architectures for Lazy Functional Programming Revisited
Fri, 10/10/2025 - 14:00 to 14:30
Location:
Speaker:
Rob Stewart & Craig Ramsey
Affiliation:
HWU
Synopsis:
Custom hardware architectures for functional languages enjoyed a boom in the 80s and 90s following Backus' Turing Award lecture "Can Programming Be Liberated from the von Neumann Style? A Functional Style and Its Algebra of Programs". Research interest later waned due to difficulties in matching the rapid pace of RISC processor development and compiler techniques. This talk from the EPSRC HAFLANG project re-explores these ideas in a modern landscape --- where single-thread performance of stock CPUs have begun to stagnate, but the performance of hardware prototyping platforms such as FPGAs have not. We present the Heron compute core for evaluating non-strict functional programs (Haskell), its concurrent hardware garbage collector, and our recent multi-core processor Siege, which scales both of these for energy efficient parallel computing on AMD UltraScale+ FPGA platforms.
Biography:
Rob Stewart is an Associate Professor in Computer Science at Heriot-Watt University, whose research interests are at the interface between programming language implementation, parallel computing and reconfigurable computer architectures, with applications in symbolic and statistical AI. In the past Rob worked as a postdoc working with EPS on FPGA design for image processing, and he is keen to reestablish research connections between MACS and EPS for systems research.
Craig Ramsay is a postdoc with expertise in FPGA design, DSP applications and programming language type systems. He has single handedly implemented the project's Siege multi-core processor, which for the Haskell language outperforms modern Intel CPUs and the highly optimised GHC compiler. Craig completed his PhD within the SDR Lab at the University of Strathclyde.
Website: