Wave-pipelining

The concept of wave-pipelining is based on the fact that the clock speed can be increased if the idle time of the non-critical paths can be reduced. Wave-pipelining is a technique employed to decrease the effective number of pipeline stages in a digital system without increasing the number of physical registers in the pipeline. The inherent capacitance in the combinational circuit is used as a storage element. Synchronization of different sets of data is achieved by equalizing the different data path delays in-between each combinational logic blocks. This idea was originally introduced by Cotton (1969), who named it as maximum rate pipelining. Cotton has observed that the rate at which logic can propagate through the circuit depends not only on the longest path delay but on the difference between the longest and the shortest path delays. As a result, wave-pipelining is the use of multiple coherent “waves” of data between storage elements. This is achieved by clocking the system faster than the propagation delay between registers. In fact, the clock period can be reduced as long as data from a particular clock cycle does not overwrite data from the previous clock cycle. The factor now limiting the clock period is the difference between the maximum and minimum data delays through the combinatorial block along with register setup/hold, propagation times, and unintentional clock skew.