Thermal scanning probe lithography for novel nanophotonics and nanoelectronics

Thermal scanning probe lithography (t-SPL) is a novel approach to maskless patterning of nanostructures with a broad field of applications. The technology has recently entered the lithography market as the first true alternative to electron beam lithography (EBL). In 2014, first dedicated t-SPL systems, NanoFrazors, were installed at research facilities in Europe and America by SwissLitho, a spinoff company of ETH Zurich. The technology originates from IBM Research Zurich and the IBM Millipede project [1].
The core of the technology is a heatable probe tip, which is used for patterning and simultaneous inspection of complex nanostructures [2, 3]. The heated tip shapes arbitrary high-resolution (<10 nm half-pitch) nanostructures by local decomposition and evaporation of the resist material. The patterning depth can be controlled with down to nm accuracy enabling direct patterning of 3D nanostructures in a single step.
The patterning speed of t-SPL is comparable to that of high-resolution Gaussian shaped EBL, and a scan speed of 20 mm/s with a pixel rate of 500 kHz has been demonstrated [4]. The written nanostructures are inspected by scanning them with a cold tip already during the patterning process. This high speed online metrology capability enables turnaround times of just a few seconds and significantly improves accuracy and reliability. Furthermore, new markerless stitching [5] and overlay [6, 7] methods achieving sub-5 nm accuracy have been developed.
Various pattern transfer methods based on reactive ion etching, lift-off, electroplating, directed self-assembly [8] and more have been demonstrated in combination with t-SPL. For example, parallel lines with 18.5 nm half-pitch* have been etched 65 nm deep into Si and various high resolution metal structures have been fabricated via lift-off [9]. Furthermore, t-SPL process does not involve high energy charged particles like electrons or ions, known to damage or charge up certain materials during lithography. For delicate nanoelectronic devices this can result in superior device performance. For example, top gates to an InAs nanowire device have been fabricated without trapped charge in the oxide underneath the electrodes [9]. The capability to pattern accurate 3D structures enables fabrication of nanooptical components, such as blazed gratings or spiral phase plates. The patterning speed and automation of the system allow for the realization of macroscopic structures with nanoscale resolution.

[1] A. Knoll, P. Bächtold, J. Bonan, G. Cherubini, M. Despont, U. Drechsler, ... & E. S. Eleftheriou, “Integrating nanotechnology into a working storage device,” Microelectronic Engineering, 83(4), 1692-1697, 2006.
[2] D. Pires, J. Hedrick, A. De Silva, J. Frommer, B. Gotsmann, H. Wolf, M. Despont, U. Duerig, and A. Knoll, “Nanoscale three-dimensional patterning of molecular resists by scanning probes,” Science, vol. 328, no. 5979, p. 732, 2010.
[3] A. Knoll, D. Pires, O. Coulembier, P. Dubois, J. Hedrick, J. Frommer, and U. Duerig, “Probe-based 3-d nanolithography using self-amplified depolymerization polymers,” Advanced Materials, vol. 22, no. 31, pp. 3361–3365, 2010.
[4] P. Paul, A. Knoll, F. Holzner, M. Despont, and U. Duerig, “Rapid turnaround scanning probe nanolithography,” Nanotechnology, vol. 22, p. 275306, 2011.
[5] P. Paul, A. Knoll, F. Holzner, and U. Duerig, “Field stitching in thermal probe lithography by means of surface roughness correlation,” Nanotechnology, vol. 23, no. 38, p. 385307, 2012.
[6] C. Rawlings, U. Duerig, J. Hedrick, D. Coady, and A. Knoll, “Nanometer accurate markerless pattern overlay using thermal scanning probe lithography,” Nanotechnology, IEEE Transactions on, vol. 13, no. 6, pp. 1204–1212, 2014.
[7] C. Rawlings, H. Wolf, J. Hedrick, U. Duerig and A. Knoll, “Accurate location and manipulation of nanoscaled objects buried under spin-coated films,” ACS Nano, Vol. 9, 6188-6195, 2015.
[8] F. Holzner, C. Kuemin, P.C. Paul, J.L. Hedrick, H. Wolf, N.D. Spencer, U. Duerig, and A.W. Knoll, Directed placement of gold nanorods using a removable template for guided assembly, Nano Letters, 11, 3957-3962, 2011.
[9] H. Wolf, C. Rawlings, P. Mensch, J. L. Hedrick, D. J. Coady, U. Duerig, and A. W. Knoll, “Sub-20 nm silicon patterning and metal lift-off using thermal scanning probe lithography,” Journal of Vacuum Science & Technology B, vol. 33, no. 2, p. 02B102, 2015.
*More recently 13.8 nm half-pitch have been transferred in Si (not yet published).